1. Field of the Invention
This invention relates to a voltage controlled oscillator (VCO) fabricated into a semiconductor integrated circuit, which is suitably used for a phase locked loop (PLL).
2. Description of the Related Art
A conventional VCO is disclosed in Japanese Patent Application Laid-Open Publication No. 59-62215, which is arranged as shown in FIG. 1. In the figure, reference numeral 101 designates an input terminal for control voltage Vin, and M1 designates an input N channel MOS transistor. P channel MOS transistors M2 and M3 make up a current mirror load circuit. P channel MOS transistor M4 and N channel MOS transistor M5 make up a first CMOS inverter INV1, with first capacitor C1 being connected between the output terminal 102 and ground. P channel MOS transistor M6 and N channel MOS transistor M7 cooperate to form a second CMOS inverter INV2, with second capacitor C2 being connected between the output terminal 103 and ground. First voltage comparator 104 is connected to the output terminal 102 of first CMOS inverter INV1, while second voltage comparator 105 is coupled with the output terminal 103 of second CMOS inverter INV2. The output terminals of voltage comparators 104 and 105 are respectively connected to the reset and set input terminals of RS flip-flop F/F. The set and reset output terminals Q and Q of this flip-flop F/F are respectively connected to the input terminals of first and second CMOS inverters INV1 and INV2. The output signal from reset output terminal Q is inverted by inverter 106, and output as output voltage Vout.
The operation of the VCO of FIG. 1 thus arranged will be described in brief. An input current, which depends on control input voltage Vin, flows through input transistor M1. A current, which is equal to the input current, is fed by output transistor M3 of the current mirror circuit into CMOS inverters INV1 and INV2. In an initial state, if the output terminals Q and Q of the flip-flop F/F are respectively low "L" in level and high "H" in level, transistors M4 and M7 are turned on, whereas transistors M5 and M6 are turned off. Under this condition, current I from current source transistor M3 charges first capacitor C1 through the transistor M4 being now in an on state. When the terminal voltage across first capacitor C1 exceeds threshold voltage Vth1 of voltage comparator 104, the output of first voltage comparator 104 becomes high in level, and the output logic level of flip-flop F/F is inverted so that the output signals of the flip-flop F/F are "H" and "L", respectively. Therefore, the transistors M4 and M7 in first and second CMOS inverters INV1 and INV2 are turned off, and the transistors M5 and M6 are turned on. As a result, current I charges second capacitor C2 through the transistor M6 being now in an on state. The charges in first capacitor C1 are discharged through transistor M5 to a ground terminal. When the terminal voltage across second capacitor C2 exceeds the threshold voltage Vth2 (=Vth1) of second voltage comparator 105, the output of second voltage comparator 105 becomes high in level, the output logic level of flip-flop F/F is inverted so that the output signals of the flip-flop F/F are "L" and "H", respectively. Therefore, the transistors M4 and M7 are returned in their operation state to an on state, and the transistors M5 and M6 are returned to an off state. A sequence of the above operations is repeated, so that voltage Vout at a frequency, which depends on the repeated operation, appears at the output terminal of inverter 106. The oscillating frequency f is given by EQU f=1/2CVref (1)
where C is capacitance of each of capacitors C1 and C2 (C=C1=C2), and Vref=threshold voltage of each of voltage comparators 104 and 105. (Vref=Vth1=Vth2). In fabricating the VCO into an LSI (large scale integrated circuit), a variance in process parameters is inevitable. The parameter variance leads to variances in the gate length of MOS transistors, threshold value, and gate oxide film thickness of the fabricated MOS transistors. Therefore, those factors C and Vref in the equation (1) greatly vary, and consequently the output frequency "f" also greatly varies. When such a VCO is incorporated into a PLL system, the characteristics of the PLL system may be degraded, and the production yield of the systems is also reduced.